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Instruction set architecture
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#	Item
481	AMX™ Timing Guide and Data for AMX CFire Multitasking Executive First Printing: June 1, 1999 Add to Reading List Source URL: www.kadak.com Language: English - Date: 2002-11-01 16:04:00 Computing Classes of computers Computer memory AMC AMX Coupes CPU cache Instruction set Superscalar Microarchitecture Computer hardware Computer architecture Central processing unit
482	MIPS R5000 Microprocessor Technical Backgrounder Performance: SPECint95 Add to Reading List Source URL: www.sgidepot.co.uk Language: English - Date: 2008-04-15 15:08:30 MIPS architecture Central processing unit R4000 R4600 R8000 CPU cache R10000 R2000 Reduced instruction set computing Computer hardware Computer architecture R5000
483	SuperH™ (SH) 32-Bit RISC MCU/MPU Series SH7750 High-Performance RISC Engine Programming Manual Add to Reading List Source URL: mc.pp.se Language: English - Date: 1999-12-02 19:29:57 Central processing unit Instruction set architectures Virtual memory Computer memory Memory management unit SuperH CPU cache Reduced instruction set computing Addressing mode Computer architecture Computer hardware Computing
484	SITCPU MISC Software MapSITCPU G-Bus Read Map: g@0 read Interrupt Control and Status Add to Reading List Source URL: epact2.gsfc.nasa.gov Language: English - Date: 2003-07-25 08:22:36 Microcontrollers Universal asynchronous receiver/transmitter Instruction set architectures Central processing unit TI MSP430 Computer architecture Data transmission Interrupts
485	General overview The MP3 cartridge contains an AtMega644 processor together with a VS1011 MP3 decoder. All registers of the decoder are shadowed by the AtMega and can be read by the MSX without additional wait states. Af Add to Reading List Source URL: map.grauw.nl Language: English - Date: 2014-12-07 09:00:39 I²C Zilog Z80 Serial Peripheral Interface Bus Processor register Computing IBM PC compatibles Instruction set architectures Graphics chips Computer architecture Computer hardware Central processing unit
486	Page 1 Vector Rewrite Attack Exploitable NULL Pointer Vulnerabilities on ARM and XScale Architectures Barnaby Jack Add to Reading List Source URL: cansecwest.com Language: English - Date: 2008-06-07 19:30:50 Pointer Interrupt vector Vector ARM architecture INT Interrupt Instruction set Interrupt vector table Computer architecture Interrupts Reset vector
487	MIPS R5000 Microprocessor Technical Backgrounder Performance: SPECint95 Add to Reading List Source URL: vintagecomputers.info Language: English - Date: 1999-05-17 08:56:29 MIPS architecture Central processing unit R4000 R4600 R8000 CPU cache R10000 R2000 Reduced instruction set computing Computer hardware Computer architecture R5000
488	Verifying the ARM Block Data Transfer Instructions Anthony Fox Computer Laboratory, University of Cambridge Abstract The hol-4 proof system has been used to formally verify the correctness of the ARM6 micro-architecture. Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2004-05-10 09:42:53 Machine code Assembly languages Central processing unit ARM architecture Addressing mode Processor register NOP DLX Computer architecture Computing Instruction set architectures
489	AMX™ Timing Guide and Data for AMX 386/ET Multitasking Executive First Printing: Add to Reading List Source URL: www.kadak.com Language: English - Date: 2002-11-01 18:01:00 Computing Computer memory AMC AMX Coupes CPU cache Instruction set Superscalar Microarchitecture Computer hardware Computer architecture Central processing unit
490	VMIPS Programmer’s Manual 1 This is the VMIPS Programmer’s Manual, Sixth Edition, for version 1.5. c 2001, 2002, 2004, 2009, 2014 Brian R. Gaeke. For information about Add to Reading List Source URL: www.dgate.org Language: English - Date: 2014-11-17 04:54:08 Computing MIPS architecture Instruction set Pointer Exception handling Page Assembly language R4000 Translation lookaside buffer Computer architecture Central processing unit Computer hardware

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